The present invention relates generally to channel banks for digital transmission, and more particularly to maintenance of digital circuits of a TDM (time-division multiplex) demultiplexer at one of the TDM hierarchical levels.
As illustrated in FIG. 1, a TDM demultiplexer currently employed at the primary level of the TDM hierarchy includes a plurality of line interfaces 50 at which incoming signals are received through high-speed digital transmission lines. Each line interface 50 is provided with a fault detector 51 which detects a fault in the associated transmission line. A clamp circuit 52 is connected in the transmission line to clamp it to a specified logic level or a series of different logic levels in response to the detection of a line fault by the fault detector 51. The outputs of the clamp circuits 52 are coupled to a time division multiplexer 53 where the incoming signals are multiplexed into a series of TDM frames, which is applied to a time division switch 54. In response to a switching signal from a time slot memory 55, the time slots of each incoming frame are interchanged by the time division switch 54 according to predetermined relationships between the incoming time slots of the high-speed digital circuits and the outgoing time slots of low-speed analog circuits. The slot-interchanged TDM frames are demultiplexed by demultiplexer 56 into individual frames, which are supplied respectively to low-speed interfaces 57 to which the analog circuits are terminated. Each of the low-speed interfaces constantly monitors the incoming signal and, on detecting a continuous string of specified logic levels, recognizes that a line fault has occurred in the associated high-speed digital circuit and sends a line-fault indication to the associated low-speed circuit. In some applications, time division switch 54 includes circuitry that constantly monitors the contents of all time slots and, on detecting a continuous string of such logic levels, converts it to a predetermined code. On detecting such a code, each low-speed interface sends a fault-indication in a format which can be decoded by terminal systems.
However, each low-speed interface must be provided with decoder circuitry having powerful error detection and correction capabilities and precision timing control in order to perform the discrimination of specified logic levels from those of data signals and the conversion of the discriminated logic levels to the format of the terminal systems.